pub const periph_interrput_t_ETS_SPI_MEM_REJECT_CACHE_INTR_SOURCE: u32 = 40; // 40u32
Expand description
< interrupt of SPI0 Cache access and SPI1 access rejected, LEVEL
pub const periph_interrput_t_ETS_SPI_MEM_REJECT_CACHE_INTR_SOURCE: u32 = 40; // 40u32
< interrupt of SPI0 Cache access and SPI1 access rejected, LEVEL