SPI peripheral control
SPI0 is reserved for accessing flash and sram and therefore not usable for other purposes. SPI1 shares its external pins with SPI0 and therefore has severe restrictions in use.
SPI2 & 3 can be used freely.
The CS pin can be controlled by hardware on esp32 variants (contrary to the description of embedded_hal).
Look at the following table to determine which driver best suits your requirements:
|SpiDeviceDriver::new||SpiDeviceDriver::new (no CS)||SpiSoftCsDeviceDriver::new||SpiBusDriver::new|
|Managed CS||Hardware||N||Software triggered||N|
|4-6 devices||Only on esp32CX||N||Y||N|
|More than 6||N||N||Y||N|
- True non-blocking async possible only when all devices attached to the SPI bus are used in async mode (i.e. calling methods
xxx_async()instead of their blocking
The [Transfer::transfer], [Write::write] and [WriteIter::write_iter] functions lock the APB frequency and therefore the requests are always run at the requested baudrate. The primitive [FullDuplex::read] and [FullDuplex::send] do not lock the APB frequency and therefore may run at a different frequency.
- Quad SPI
- Slave SPI
- SPI configuration
- SPI transaction operation.
- A marker interface implemented by all SPI peripherals except SPI1 which should use a fixed set of pins