Module esp_idf_hal::spi
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SPI peripheral control
SPI0 is reserved for accessing flash and sram and therefore not usable for other purposes. SPI1 shares its external pins with SPI0 and therefore has severe restrictions in use.
SPI2 & 3 can be used freely.
The CS pin can be controlled by hardware on esp32 variants (contrary to the description of embedded_hal).
Look at the following table to determine which driver best suits your requirements:
| SpiDeviceDriver::new | SpiDeviceDriver::new (no CS) | SpiSoftCsDeviceDriver::new | SpiBusDriver::new | ||
|---|---|---|---|---|---|
| managed cs | hardware | - | software triggered | - | |
| 1 device | x | x | x | x | |
| 1-3 devices | x | - | x | - | |
| 4-6 devices | only on esp32c* | - | x | - | |
| more than 6 | - | - | x | - | |
| Dma | - | - | - | - | |
| polling transmit | x | x | x | x | |
| isr transmit | - | - | - | - | |
| async ready | - | - | - | - |
The [Transfer::transfer], [Write::write] and [WriteIter::write_iter] functions lock the APB frequency and therefore the requests are always run at the requested baudrate. The primitive [FullDuplex::read] and [FullDuplex::send] do not lock the APB frequency and therefore may run at a different frequency.
TODO
- Quad SPI
- Slave SPI
Modules
- SPI configuration
Structs
Enums
Traits
- A marker interface implemented by all SPI peripherals except SPI1 which should use a fixed set of pins